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minhlee's avatar
minhlee
Icon for New Contributor rankNew Contributor
2 years ago
Solved

I/O assignment analysis fail Quartus Prime Lite 23.1 for CycloneV

Hi everyone, currently I am creating my own SoC system. I have run Analysis and Synthesis successfully, then I run tcl script hps_sdram_p0_parameters.tcl and hps_sdram_p0_pin_assignments.tcl respecti...
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  • ShengN_altera's avatar
    ShengN_altera
    2 years ago

    Hi,


    The error due to the width mismatch between the ports of top module DE10_NANO_SoC_GHRD.v and the ports of msdma_fpga.

    Modify the lines below in DE10_NANO_SoC_GHRD.v then there'll be no error anymore after running the tcl script and I/O assignment analysis:

    Line 29: output [/*14*/12: 0] HPS_DDR3_ADDR,

    Line 37: inout [/*31*/7: 0] HPS_DDR3_DQ,

    Line 39: inout /*[ 3: 0]*/ HPS_DDR3_DQS_P,


    Thanks,

    Regards,

    Sheng


ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,


The error due to the width mismatch between the ports of top module DE10_NANO_SoC_GHRD.v and the ports of msdma_fpga.

Modify the lines below in DE10_NANO_SoC_GHRD.v then there'll be no error anymore after running the tcl script and I/O assignment analysis:

Line 29: output [/*14*/12: 0] HPS_DDR3_ADDR,

Line 37: inout [/*31*/7: 0] HPS_DDR3_DQ,

Line 39: inout /*[ 3: 0]*/ HPS_DDR3_DQS_P,


Thanks,

Regards,

Sheng


  • minhlee's avatar
    minhlee
    Icon for New Contributor rankNew Contributor
    2 years ago

    Nice, thank you very much.