Forum Discussion
New ContributorI/O assignment analysis fail Quartus Prime Lite 23.1 for CycloneV
Hi,
The error due to the width mismatch between the ports of top module DE10_NANO_SoC_GHRD.v and the ports of msdma_fpga.
Modify the lines below in DE10_NANO_SoC_GHRD.v then there'll be no error anymore after running the tcl script and I/O assignment analysis:
Line 29: output [/*14*/12: 0] HPS_DDR3_ADDR,
Line 37: inout [/*31*/7: 0] HPS_DDR3_DQ,
Line 39: inout /*[ 3: 0]*/ HPS_DDR3_DQS_P,
Thanks,
Regards,
Sheng
Super ContributorIt looks like you may have made manual pin assignments to pins dedicated to the HPS, like those HDMI signals as well as assignments to the dedicated JTAG pins. What does your Pin Planner look like?
minhleeHi @strell, here is my zip file contain my project. Basically, I am currently learning how to use mSGDMA core from this tutorial: https://blog.reds.ch/?p=835 to access DRAM from FPGA in my de10 nano.
