Initialize parameter of an array type

Try this; it doesn't give me any errors.

parameter bit [7:0] RVSeq [11:0] = '{8'h40, 8'h52, 8'h56, 8'h30, 8'h30, 8'h34, 8'h30, 8'h30, 8'h35, 8'h30, 8'h31, 8'h2A};

Note that it's SystemVerilog syntax. You can change "bit" to "reg" or whatever type you want. Quartus just complains if no type is given.

Hi,

Thanks for your reply. It does not work in Verilog. It gives me compilation error of:

error (10170): verilog hdl syntax error at rs232.v(22) near text '

Hi,

I'm doing VHDL but on first sight it might be the "'" at "{" that is claimed.. Maybe worth removing this (the "'" between "8" and "h" to identify the number as hexadecimal is accepted I think).

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Hi,

Thanks for your reply. It does not work in Verilog. It gives me compilation error of:

error (10170): verilog hdl syntax error at rs232.v(22) near text '

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That was why I mentioned that it was SystemVerilog syntax. Quartus supports it, but it needs to be told that the file is SystemVerilog or else it will give errors because that syntax does not exist in regular Verilog. If you rename RS232.v to RS232.sv, Quartus will treat the file as SystemVerilog automatically.

If you explicitly need Verilog and not SystemVerilog (for compatibility with Xilinx's ISE tool that does not allow SystemVerilog, for example), I don't have a solution. This kind of thing is why I prefer SystemVerilog whenever possible.

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Hi,

I'm doing VHDL but on first sight it might be the "'" at "{" that is claimed.. Maybe worth removing this (the "'" between "8" and "h" to identify the number as hexadecimal is accepted I think).

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Hi, thanks for your reply. I think i would use back VHDL in this case to solve my problem. I believe in verilog we cannot do this kind of array initialization as easy as this. However, my application requires me to do so. Thanks again!

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That was why I mentioned that it was SystemVerilog syntax. Quartus supports it, but it needs to be told that the file is SystemVerilog or else it will give errors because that syntax does not exist in regular Verilog. If you rename RS232.v to RS232.sv, Quartus will treat the file as SystemVerilog automatically.

If you explicitly need Verilog and not SystemVerilog (for compatibility with Xilinx's ISE tool that does not allow SystemVerilog, for example), I don't have a solution. This kind of thing is why I prefer SystemVerilog whenever possible.

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Hi, thanks for your reply. I would use VHDL in this case since i am more familiar with it. Thanks again!