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Altera_Forum
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12 years ago

Initialize parameter of an array type

Hi, In VHDL, we can have something like this: TYPE memory1 is array (0 to 11) of std_logic_vector(7 downto 0); constant RVSeq: memory1 := (X"40", X"52", X"56", X"30", X"30", X"34", X"30"...
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Altera_Forum
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12 years ago

Try this; it doesn't give me any errors.

parameter bit [7:0] RVSeq [11:0] = '{8'h40, 8'h52, 8'h56, 8'h30, 8'h30, 8'h34, 8'h30, 8'h30, 8'h35, 8'h30, 8'h31, 8'h2A};

Note that it's SystemVerilog syntax. You can change "bit" to "reg" or whatever type you want. Quartus just complains if no type is given.