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Altera_Forum's avatar
Altera_Forum
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12 years ago

Initialize parameter of an array type

Hi, In VHDL, we can have something like this: TYPE memory1 is array (0 to 11) of std_logic_vector(7 downto 0); constant RVSeq: memory1 := (X"40", X"52", X"56", X"30", X"30", X"34", X"30"...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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Hi,

I'm doing VHDL but on first sight it might be the "'" at "{" that is claimed.. Maybe worth removing this (the "'" between "8" and "h" to identify the number as hexadecimal is accepted I think).

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Hi, thanks for your reply. I think i would use back VHDL in this case to solve my problem. I believe in verilog we cannot do this kind of array initialization as easy as this. However, my application requires me to do so. Thanks again!