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Hi,
Thanks for your reply. It does not work in Verilog. It gives me compilation error of:
error (10170): verilog hdl syntax error at rs232.v(22) near text ' --- Quote End ---
That was why I mentioned that it was SystemVerilog syntax. Quartus supports it, but it needs to be told that the file is SystemVerilog or else it will give errors because that syntax does not exist in regular Verilog. If you rename RS232.v to
RS232.sv, Quartus will treat the file as SystemVerilog automatically.
If you explicitly need Verilog and not SystemVerilog (for compatibility with Xilinx's ISE tool that does not allow SystemVerilog, for example), I don't have a solution. This kind of thing is why I prefer SystemVerilog whenever possible.
Honored Contributor
