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Altera_Forum
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12 years ago

Initialize parameter of an array type

Hi, In VHDL, we can have something like this: TYPE memory1 is array (0 to 11) of std_logic_vector(7 downto 0); constant RVSeq: memory1 := (X"40", X"52", X"56", X"30", X"30", X"34", X"30"...
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Altera_Forum
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12 years ago

Hi,

Thanks for your reply. It does not work in Verilog. It gives me compilation error of:

error (10170): verilog hdl syntax error at rs232.v(22) near text '