Implementing static RAMs on Quartus block schematics (targeting MAX10)
Hi all,
this is my first post here, very happy and excited to be part of this community
I'm doing my first FPGA project with a MAX10M08SCE144C8G device, since I'm not (yet) familiar with HDL (Verilog or VHDL) I'm tranlsating my TTL schematics to Quartus Prime (ver 17) block schematics.My design has some static RAMs that I'm unable to properly implement.I tried the IP megafunction but the resulting symbol has separate DATA INPUT and OUTPUT bus (while the real RAM has a single tristate bus), when I try to compie I get some errors complaining about tristate buffer (FPGA cannot have them internally IIRC).I also tried some Verilog/VHD models with single DATA bus I found on the net but none works.
I attach the snippet of the TTL schematics with RAMs hoping someone will help me.Thanks in advance.