Implementing static RAMs on Quartus block schematics (targeting MAX10)

Hi,
main problem in emulating static RAM isn't the bidirectional data bus, it's the fact that FPGA block RAM is synchronous, it uses a clock, at least all inputs (address, data, WE) are registered. This allows faster operation than asynchronous RAM, but external logic will look different.
As you already mentioned, there's no bidirectional bus inside the FPGA, but it can be emulated if it serves a purpose. External I/O pins can of course implement bidirectional I/O with tri-state, similar to discussed RAM.