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Valerius's avatar
Valerius
Icon for New Contributor rankNew Contributor
1 year ago

Implementing static RAMs on Quartus block schematics (targeting MAX10)

Hi all, this is my first post here, very happy and excited to be part of this community I'm doing my first FPGA project with a MAX10M08SCE144C8G device, since I'm not (yet) familiar with HDL (Veril...
Hdl
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
1 year ago

As mentioned, there is no tristate logic internal to the FPGA fabric, so your design is going to have to change, either by replacing with synchronous RAM blocks, as mentioned, or just registers.