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Altera_Forum
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11 years ago

Implementing PCIe with qsys in quartus 14.0

I am trying to generate PCIe from IP catalog, and generated its qsys system. Targeting Stratix V 5SGXEA7N2F40C2. During compilation run its passing Analysis & Synthesis, Fitter, Assembler but when I check compilation report, for 'TimeQuest Timing Analyzer' it shows error for Unconstrained Paths. But Assembler stage passed and generated .sof programming file. So why I am getting that error? I did not change anything in the design/constraint files, design is default generated out of Quartus. Is that error real or can be ignored and I can program the .sof?

Also in left hand side - Task window (where it shows the Flow progress) it does not show the error.

Please find the attached screenshot.

Looking forward for the reply ASAP, thank you!

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Your screen capture does not show enough information.

    Run TimeQuest and have it report unconstrained paths. From that you can tell what signal it believes is an unconstrained clock.

    I wrote some notes regarding the issues with timing failures in earlier versions of this core, but have not looked at 14.0, perhaps this thread and the associated PDF has some relevant info ...

    http://www.alteraforum.com/forum/showthread.php?t=35678

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Thank you for your quick reply.

    I ran TimeQuest to check the unconstrained paths but it does not report any, that's why I am not able to understand what is wrong or if I am following correct things.

    Below is the TimeQuest snapshot, I am new to Quartus and I hope I am doing the correct thing.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    I ran TimeQuest to check the unconstrained paths but it does not report any, that's why I am not able to understand what is wrong or if I am following correct things.

    Below is the TimeQuest snapshot, I am new to Quartus and I hope I am doing the correct thing.

    --- Quote End ---

    You're looking at the wrong place in the TimeQuest GUI. Once you run that task, there will be several folders generated in the GUI near the top-left. Click through those folders and you'll see the paths identified.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Well, I see some folders created at left side but they are not for the unconstrained report run, looks like all those for some or the other report run. I am not sure exactly where I need to check for the unconstrained paths.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    That is the tasks pane. The report pane usually shows up above the tasks pane (the one you just posted). Rather than screen shot the pane, capture the whole TimeQuest GUI. Perhaps you've closed the results pane and it does not show up.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Ok, got it here is the Report pane. For unconstrained clock I have added its constraint to sdc so it is solved but it still complaining about many unconstrained IO ports and paths. So if I am generating design out of quartus then why all these constraint errors, isn't it should have everything auto generated for default design and run though without errors?

    So just to verify: if I have created pcie ip through ip catalog and then to create its example design I have to follow the qsys flow right, that is the only way?
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    For unconstrained clock I have added its constraint to sdc so it is solved but it still complaining about many unconstrained IO ports and paths. So if I am generating design out of quartus then why all these constraint errors, isn't it should have everything auto generated for default design and run though without errors?

    --- Quote End ---

    My experience with the core was that it also generated lots of errors, so I was pretty disappointed, and decided not to use the PCIe interface on the FPGA.

    I'm not sure what the function of most of the unconstrained paths is, you'll have to read the PCIe users guide for your device. If you can find an example design that uses the same FPGA as your board, you can try synthesizing that to see if it has errors; if it does not, you can look at its SDC constraints.

    You could also file a Service Request with Altera.

    --- Quote Start ---

    So just to verify: if I have created pcie ip through ip catalog and then to create its example design I have to follow the qsys flow right, that is the only way?

    --- Quote End ---

    You can create a PCIe core with Avalon-ST interfaces, but then you have to develop the interface logic. The "easy" way is supposed to be via Qsys, but if Altera's tools do not generate IP that builds without warnings, its very annoying.

    Cheers,

    Dave