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Altera_Forum
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11 years ago

Implementing PCIe with qsys in quartus 14.0

I am trying to generate PCIe from IP catalog, and generated its qsys system. Targeting Stratix V 5SGXEA7N2F40C2. During compilation run its passing Analysis & Synthesis, Fitter, Assembler but when I ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Ok, got it here is the Report pane. For unconstrained clock I have added its constraint to sdc so it is solved but it still complaining about many unconstrained IO ports and paths. So if I am generating design out of quartus then why all these constraint errors, isn't it should have everything auto generated for default design and run though without errors?

So just to verify: if I have created pcie ip through ip catalog and then to create its example design I have to follow the qsys flow right, that is the only way?