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Altera_Forum
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11 years ago

Implementing PCIe with qsys in quartus 14.0

I am trying to generate PCIe from IP catalog, and generated its qsys system. Targeting Stratix V 5SGXEA7N2F40C2. During compilation run its passing Analysis & Synthesis, Fitter, Assembler but when I ...
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Altera_Forum
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11 years ago

Your screen capture does not show enough information.

Run TimeQuest and have it report unconstrained paths. From that you can tell what signal it believes is an unconstrained clock.

I wrote some notes regarding the issues with timing failures in earlier versions of this core, but have not looked at 14.0, perhaps this thread and the associated PDF has some relevant info ...

http://www.alteraforum.com/forum/showthread.php?t=35678

Cheers,

Dave