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For unconstrained clock I have added its constraint to sdc so it is solved but it still complaining about many unconstrained IO ports and paths. So if I am generating design out of quartus then why all these constraint errors, isn't it should have everything auto generated for default design and run though without errors?
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My experience with the core was that it also generated lots of errors, so I was pretty disappointed, and decided not to use the PCIe interface on the FPGA.
I'm not sure what the function of most of the unconstrained paths is, you'll have to read the PCIe users guide for your device. If you can find an example design that uses the same FPGA as your board, you can try synthesizing that to see if it has errors; if it does not, you can look at its SDC constraints.
You could also file a Service Request with Altera.
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So just to verify: if I have created pcie ip through ip catalog and then to create its example design I have to follow the qsys flow right, that is the only way?
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You can create a PCIe core with Avalon-ST interfaces, but then you have to develop the interface logic. The "easy" way is supposed to be via Qsys, but if Altera's tools do not generate IP that builds without warnings, its very annoying.
Cheers,
Dave
Honored Contributor
