Implementation and Timing of Reset Circuits

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Hi,

An interesting article, I guess you are the author.

I understand that in principle there are only two types of reset:

1)synchronous reset(gated with data) and

2)asynchronous reset(directly connected to port of flipflops)

It is also well-known that reset removal must be synchronised to its registers clock domain or else you will get problems especially as power-up differences of operation. I normally use a two stage synchroniser. The method explained in fig 16 of this article is interesting but I haven't tried it yet.

However, the article doesn't define clearly the LAB-wide synchronous reset and it implies at times that it is not gated but I assume it is also gated. I looked at the 766 pages of stratix ii handbook and there was only one occurence of synclr which was in a diagram same as your diagram.

There is no mention of chip-wide reset. I have never used it and I don't know it resets the firmware only or the configuration as well.

For power-up reset, I can use internal counter that counts up to a maximum and stops and then I can do my reset work on its count values which yields a synchronous reset that is connected to asynchronous ports.

As to external reset(synchronised or not), I believe in most cases it is waste of design since you can do a nice internal reset including power-up reset as mentioned above.

Thanks for the article.

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Hi，

Do the "reset removal must be synchronised " mean asynchronous reset input and synchrous reset output(or release)? Like below code implementations( and the attached block image):

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

entity Rst_Async2Sync is

port (

clkin : in std_logic;

async_rst : in std_logic;

sync_rst : out std_logic

);

end Rst_Async2Sync;

architecture rtl of Rst_Async2Sync is

signal Sync_rst1,Sync_rst2: std_logic;

begin

process(clkin,async_rst)

begin

if async_rst='1' then

Sync_rst1 <= '1';

elsif clkin'event and clkin='1' then

Sync_rst1 <= '0';

end if;

end process;

process(clkin,async_rst)

begin

if async_rst='1' then

Sync_rst2 <= '1';

elsif clkin'event and clkin='1' then

Sync_rst2 <= Sync_rst1;

end if;

end process;

sync_rst <= Sync_rst2;

end ;

Hi all,

I used asynchronous reset that is resynchronized when deasserted.

Clock is running at 200 MHz in a stratixIV (class -3) and I am quite surprised to see that some pathes are very hard to route for quartus 9.1 :

After being synchronized with the clock, reset is put on a global (about 2ns delay: seems to be ok) and even being routed on a global, there are still some 2ns delay time elsewhere in the reset path, especially when I need to reset registers that are close (or inside) io buffer. With a period equal to 5ns, it is quite hard to route these paths and when registers have inverted clock it is even impossible to route without recovery violation.

is it normal to have 2ns delay time in recovery path ? Is it due to the fact that registers to reset are inside io buffer ? Do I have move out these registers ?

Thanks a lot for your help

Hi All,

When using the free-running counter to do a reset on powerup when the count reaches some value what is used to ensure the counter logic is reset to a known state before the count begins ??

If count starts from some uknown state presumable result is unpredictable.

Contrary to ASICs, FPGA always start in a known state. You can give a specific startup value for your counter.

It can also be an idea to use the pll's loked signal as an asynchronous reset for your counter, to be sure you never start your design before the clocks are correct.

Thanks Daixiwen,

I'm sure you're right but this seems at odds with all that is taught about the importance of having a reset.

We are saying "not required" for the reset countdown timer :)