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Altera_Forum
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17 years ago

Implementation and Timing of Reset Circuits

Most circuit designs employing FPGAs and ASICs are synchronous systems using a large number of flip-flops or registers. It is usually important that these synchronous elements are capable of startin...
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Altera_Forum
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13 years ago

Hi All,

When using the free-running counter to do a reset on powerup when the count reaches some value what is used to ensure the counter logic is reset to a known state before the count begins ??

If count starts from some uknown state presumable result is unpredictable.