Implementation and Timing of Reset Circuits

Hi all,

I used asynchronous reset that is resynchronized when deasserted.

Clock is running at 200 MHz in a stratixIV (class -3) and I am quite surprised to see that some pathes are very hard to route for quartus 9.1 :

After being synchronized with the clock, reset is put on a global (about 2ns delay: seems to be ok) and even being routed on a global, there are still some 2ns delay time elsewhere in the reset path, especially when I need to reset registers that are close (or inside) io buffer. With a period equal to 5ns, it is quite hard to route these paths and when registers have inverted clock it is even impossible to route without recovery violation.

is it normal to have 2ns delay time in recovery path ? Is it due to the fact that registers to reset are inside io buffer ? Do I have move out these registers ?

Thanks a lot for your help