Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Implementation and Timing of Reset Circuits

Most circuit designs employing FPGAs and ASICs are synchronous systems using a large number of flip-flops or registers. It is usually important that these synchronous elements are capable of startin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Contrary to ASICs, FPGA always start in a known state. You can give a specific startup value for your counter.

It can also be an idea to use the pll's loked signal as an asynchronous reset for your counter, to be sure you never start your design before the clocks are correct.