--- Quote Start ---
Hi,
An interesting article, I guess you are the author.
I understand that in principle there are only two types of reset:
1)synchronous reset(gated with data) and
2)asynchronous reset(directly connected to port of flipflops)
It is also well-known that reset removal must be synchronised to its registers clock domain or else you will get problems especially as power-up differences of operation. I normally use a two stage synchroniser. The method explained in fig 16 of this article is interesting but I haven't tried it yet.
However, the article doesn't define clearly the LAB-wide synchronous reset and it implies at times that it is not gated but I assume it is also gated. I looked at the 766 pages of stratix ii handbook and there was only one occurence of synclr which was in a diagram same as your diagram.
There is no mention of chip-wide reset. I have never used it and I don't know it resets the firmware only or the configuration as well.
For power-up reset, I can use internal counter that counts up to a maximum and stops and then I can do my reset work on its count values which yields a synchronous reset that is connected to asynchronous ports.
As to external reset(synchronised or not), I believe in most cases it is waste of design since you can do a nice internal reset including power-up reset as mentioned above.
Thanks for the article.
--- Quote End ---
Hi，
Do the "reset removal must be synchronised " mean asynchronous reset input and synchrous reset output(or release)? Like below code implementations( and the attached block image):
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity Rst_Async2Sync is
port (
clkin : in std_logic;
async_rst : in std_logic;
sync_rst : out std_logic
);
end Rst_Async2Sync;
architecture rtl of Rst_Async2Sync is
signal Sync_rst1,Sync_rst2: std_logic;
begin
process(clkin,async_rst)
begin
if async_rst='1' then
Sync_rst1 <= '1';
elsif clkin'event and clkin='1' then
Sync_rst1 <= '0';
end if;
end process;
process(clkin,async_rst)
begin
if async_rst='1' then
Sync_rst2 <= '1';
elsif clkin'event and clkin='1' then
Sync_rst2 <= Sync_rst1;
end if;
end process;
sync_rst <= Sync_rst2;
end ;
Honored Contributor
