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Altera_Forum
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17 years ago

Implementation and Timing of Reset Circuits

Most circuit designs employing FPGAs and ASICs are synchronous systems using a large number of flip-flops or registers. It is usually important that these synchronous elements are capable of startin...
Altera_Forum's avatar
Altera_Forum
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13 years ago

I just answered your question about having a known state at power up. I still think it's better to use an asynchronous reset mechanism, just to be sure the FPGA design isn't enabled before the clock is right and avoid possible problems due to bad timing.