Implement mux using for loop

It has to be implemented as a priority encoder because i has to keep being compared to mux_slct. Why not just use a case statement?

Hi sstrell,

type array_type is array (7 downto 0) of std_logic_vector(15 downto 0);
signal mux_in:    array_type;
signal mux_slct: unsigned(2 downto 0);
signal mux_out: std_logic_vector(15 downto 0);
...
p_mux : process(mux_slct,mux_in)
begin
   case mux_slct is
      when 0 => mux_out <= mux_in(0);
      when 1 => mux_out <= mux_in(1);
      when 2 => mux_out <= mux_in(2);
      when 3 => mux_out <= mux_in(3);
      when 4 => mux_out <= mux_in(4);
      when 5 => mux_out <= mux_in(5);
      when 6 => mux_out <= mux_in(6);
      when 7 => mux_out <= mux_in(7);
      when others => mux_out <= (others=>'0');
   end case;
end process p_mux;

This is because it fits the template for a priority encoder. Multiple ifs, with a default if one isnt hit, even though they are mutually exclusive. The technology view may have worked properly, but wont look nice.

Hi Tricky,

type array_type is array (5 downto 0) of std_logic_vector(15 downto 0);
signal mux_in:    array_type;
signal mux_slct: unsigned(2 downto 0);
signal mux_out: std_logic_vector(15 downto 0);
...
-- no problem with that
mux_slct  <= "011";
mux_out1 <= mux_in(to_integer(mux_slct);
-- what about this situation
mux_slct  <= "111";
mux_out2 <= mux_in(to_integer(mux_slct);

p_mux : process(mux_slct,mux_in)
begin
   if(mux_slct < mux_in'length) then
      mux_out <= mux_in(to_integer(mux_slct));
   else
      mux_out <= (others<='0');
   end if;
end process p_mux;

When building (having just tried it) it fills the non-existing entries with 0's without modifying my code (other than the array size)

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package test_pkg is
type array_type is array (5 downto 0) of std_logic_vector(15 downto 0);
end package test_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.test_pkg.all;
entity mux_test is
  port (
    mux_in    : in  array_type;
    mux_slct  : in  unsigned(2 downto 0);
    mux_out   : out std_logic_vector(15 downto 0)
  );
end entity mux_test;
architecture rtl of mux_test is
begin
  mux_out <= mux_in( to_integer( mux_slct) );
end architecture rtl;

You said