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Altera_Forum
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8 years ago

Implement mux using for loop

Hi I think it is possible to implement a mux using a for loop like in the following example: type array_type is array (7 downto 0) of std_logic_vector(15 downto 0); signal mux_in: array...
Altera_Forum's avatar
Altera_Forum
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8 years ago

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The mux_out can be invalid for some mux_slct values if further in the pipeline this mux_out signal is not propagated in situation where mux_slct was "out of bounds". You still want to be able to test your circuit so you need a default value or the simulation will fail.

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You can use this to your advantage in simulation. The test fails, therefore there is an error in the generation of mux_slct.