--- Quote Start ---
My problem is that Quartus seems (based on RTL viewer) to synthesise it as a priority circuit which is not efficient at all.
--- Quote End ---
I couldn't believe the assumption of "inefficient" synthesis of the code in the first post. A test compilation shows that it's actually wrong.
All three variants discussed in the thread (loop, case, direct mux) end up with the same logic cell utilization and combinational delay of three LEs (with Cyclone III/IV 4-input LUT).
The only "problem" is that the RTL schematics are quite different, but the gate level isn't.
I know that it's not guaranteed to get identical gate level output for functionally equivalent logic, but it seems to work in this case.
Honored Contributor
