Forum Discussion
Altera_Forum
Honored Contributor
8 years agoYou said
--- Quote Start --- This is probably the best situation, as you wouldnt want control logic selecting a non-existing connection. --- Quote End --- The mux_out can be invalid for some mux_slct values if further in the pipeline this mux_out signal is not propagated in situation where mux_slct was "out of bounds". You still want to be able to test your circuit so you need a default value or the simulation will fail. So yeah, I'll opt for a robust solution ;-) It's just desapointing Quartus (maybe just my student version?) can't manage with the for...loop statement. I'm sure some other synthesis tools can. Thank you for your help Tricky!