Implement mux using for loop

When building (having just tried it) it fills the non-existing entries with 0's without modifying my code (other than the array size)

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package test_pkg is
type array_type is array (5 downto 0) of std_logic_vector(15 downto 0);
end package test_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.test_pkg.all;
entity mux_test is
  port (
    mux_in    : in  array_type;
    mux_slct  : in  unsigned(2 downto 0);
    mux_out   : out std_logic_vector(15 downto 0)
  );
end entity mux_test;
architecture rtl of mux_test is
begin
  mux_out <= mux_in( to_integer( mux_slct) );
end architecture rtl;