Occasional ContributorHPS -> FPGA Throughtput Experiment
Hi all,
I am attempting an experiment to calculate the throughput of the HPS -> FPGA Bridge and the Visa-versa on the Stratix 10. I decided that I would use a FIFO in Quartus Platform Designer to accomplish this, essentially writing to the FIFO from HPS until the FIFO is full and time the process from the first to last write on software. This would give me a time elapsed and a known number of bits to calculate the throughput. The same concept would be applied on the way back.
After designing a simple Qsys design using the Avalon FIFO Memory IP I noticed in the documentation given API for the IP core.
I then looked into how as it would streamline to software process. I noticed that the fucntions required two header files -
<altera_avalon_fifo_regs.h>, <altera_avalon_fifo_utils.h>
which were located at <install_dir>\quartus\sopc_builder\components\altera_avalon_fifo\HAL\inc\ ...
but when I checked this location this directory did not exist from the components folder on.
Maybe I am looking at older documentation but it foiled my plans of using the APIs.
How come I am missing this directory? Or if it is easier, how could I test the throughput in a different way? Any help on completing this experiment helps.
Thanks,
James
