EBERLAZARE_I_Intel
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Re: RVALID is high after reset on Agilex 7 M-series F2H bridge
Hi, I see in the old boot logs, the FPGA bridges are not setup yet: How's the latest boot log using the latest Quartus and U-boot? Is the bridge configured properly now? In the new U-boot, the bridge enable is added as per line 15 & 54: u-boot-socfpga/drivers/fpga/altera.c at socfpga_v2023.10 · altera-opensource/u-boot-socfpga · GitHub Okay, for these signal is more related to the HBM2 IP and how the AXI interface is defined(HBM2 IP UG): https://www.intel.com/content/www/us/en/docs/programmable/683189/23-4-19-6-1/axi-user-interface-signals.html As I couldn't find these signals in the HPS TRM for Agilex 7, for the ARLEN it is the burst length transaction (you may find it in the above link, "axi_0_0_arlen"). How is the HBM2 IP's setting on the burst length value? Anyway, I am a bit caught up on my side and the HBM2 IP is new to me too, so I may provide my responses late. Thanks for your patience.Re: RVALID is high after reset on Agilex 7 M-series F2H bridge
Hi, Just want to check if you are also using the latest versions of the source code releases, U-boot = socfpga_v2023.10 etc..? Okay, so using the GHRD from Rocketboards, the FPGA configuration is done right before "starting the kernel", including enabling the FPGA bridges: Is it possible that you check again the signals behavior after booting to Linux as root in the signal tap? That would confirm that the bridge and FPGA enable and configured and the signal should behave as it should. If you still see otherwise, let us know.Re: FW_CODE_NOT_WORKING_WHEN_CONFIGURED_FPGA_WITH_JIC_PROGRAMMING
Hi, Which Quartus version are you using? Is the Cyclone V GT custom or the dev kit version? Can you archive the Quartus design to me here? You are using the Hello World template in the Nios II SBT right? I will help you check and create the .jic on my side.Re: RVALID is high after reset on Agilex 7 M-series F2H bridge
Hi, Are you using this board?: https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agm039.html May I know how you boot up the board, using SD card etc? Can you explain briefly how you perform the reset, is it thourgh the signal tap? Also, if you do a power cycle of the board does the signal also behave the same? If you are using the above aforementioned board, we have the GSRD for it: https://www.rocketboards.org/foswiki/Documentation/AgilexSoCGSRDDEVAGM039FRe: Execute-in-place with Generic Serial Flash controller and Nios V
Hi, It is this one: https://www.intel.com/content/www/us/en/docs/programmable/726952/23-4/nios-v-processor-design-configuration-49895.html You set your flash device in the GSFI IP settings including when you try to generate the .jic file at the end of the chapter.
