james57Occasional Contributor2 years agoHPS -> FPGA Throughtput Experiment Hi all, I am attempting an experiment to calculate the throughput of the HPS -> FPGA Bridge and the Visa-versa on the Stratix 10. I decided that I would use a FIFO in Quartus Platform Designer to ac...Show More
Recent DiscussionsTiming analysis - long combinational pathThe quartus license works with version 25.0 but not with version 17.0Using Reset Release IP (Agilex, Stratix) without IP catalog via simple instantiation is ok?Power Analyzer for Cyclone 10 GXReset Release IP for Agilex needs Stratix 10 device files installed!