How to write tcl command in sdc file for generated clock inside a component?

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You can use GUI to create the clock,then copy the command to the sdc file.

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Yes, I try to use GUI “Insert Constraint”, but I can't find that wire I want in GUI. Any other approach?

Thanks very much.

Your problem is that you are trying to assign the clock to a net, and the clock is traversing through a register, which is a timing node. You cannot traverse through a timing node to do this. If you make your target of your generated clock the register bit that is driving that net, it will work as you expect.

create_generated_clock -name {clk_160ns} -source [get_ports {clk}] -divide_by 4 [get_registers {a[2]}]

(This assumes that bit 2 of your register "a" is what is driving the divide by 4 on the input clock).

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Your problem is that you are trying to assign the clock to a net, and the clock is traversing through a register, which is a timing node. You cannot traverse through a timing node to do this. If you make your target of your generated clock the register bit that is driving that net, it will work as you expect.

create_generated_clock -name {clk_160ns} -source [get_ports {clk}] -divide_by 4 [get_registers {a[2]}]

(This assumes that bit 2 of your register "a" is what is driving the divide by 4 on the input clock).

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Thanks very much, jimbo. I think I got what you mean. If still take my design as the example, in my module instance "a", I have a 2bit counter instance "counter_a" is drived by 40 ns clock, so the the 2nd bit output of "counter_a" is the clock "clk_160ns". I should write the command as:

create_generated_clock -name {clk_160ns} -source [get_ports {clk}] -divide_by 4 [get_registers {a|counter_a[2]}]

Is that right?

Thanks.

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Yes, that should work. I assume you already have a create_clock constraint for the input clock on port {clk}, right?

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Yes, I do. I will try this later, if there is still problem, I will post here again. Thanks so much.