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Altera_Forum
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13 years ago

How to write tcl command in sdc file for generated clock inside a component?

I have a system design, inside this top design, there are several components. E.g. :One of component name is "A", and its instance is "a". If there is a generated clock is clk_160ns (wire) , which is...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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Yes, that should work. I assume you already have a create_clock constraint for the input clock on port {clk}, right?

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Yes, I do. I will try this later, if there is still problem, I will post here again. Thanks so much.