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Altera_Forum
Honored Contributor
13 years ago --- Quote Start --- Your problem is that you are trying to assign the clock to a net, and the clock is traversing through a register, which is a timing node. You cannot traverse through a timing node to do this. If you make your target of your generated clock the register bit that is driving that net, it will work as you expect. create_generated_clock -name {clk_160ns} -source [get_ports {clk}] -divide_by 4 [get_registers {a[2]}] (This assumes that bit 2 of your register "a" is what is driving the divide by 4 on the input clock). --- Quote End --- Thanks very much, jimbo. I think I got what you mean. If still take my design as the example, in my module instance "a", I have a 2bit counter instance "counter_a" is drived by 40 ns clock, so the the 2nd bit output of "counter_a" is the clock "clk_160ns". I should write the command as: create_generated_clock -name {clk_160ns} -source [get_ports {clk}] -divide_by 4 [get_registers {a|counter_a[2]}] Is that right? Thanks.