How to write a verilog memory code with a inout data port

Hi all,

I was trying to write a verilog code for a memory module which has has a bidirectional inout port for the data.

But I also want to output high impedance during write or if MEM_OE(output enable) is not set. But my code as below cannot simulate the reading correctly... It outputs high impedance even after I enabled the MEM_OE and do the reading.

Plz help me, thanks in advance！

module memory_emb(address, MEM_RW, MEM_OE, MEM_DATA, clk);
input  address;
input MEM_RW, MEM_OE;
//MEM_OE=1 for memory output enable, MEM_OE=0 output=ZZZZ...
//MEM_RW=0 for read, MEM_RW=1 for write
inout  MEM_DATA;
input clk;
wire  MEM_DATA;
reg  data_out; //internal wire
reg  Memory ; 
assign MEM_DATA=(MEM_OE&&!MEM_RW)?data_out:18'bz;
always@(posedge clk)
begin
  if(!MEM_RW&&MEM_OE)
    data_out<=Memory;  
  else if(MEM_RW&&MEM_OE)
    begin
      Memory<=MEM_DATA;
     
    end
end
endmodule