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Altera_Forum
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15 years ago

How to write a verilog memory code with a inout data port

Hi all, I was trying to write a verilog code for a memory module which has has a bidirectional inout port for the data. But I also want to output high impedance during write or if MEM_OE(out...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi bark,

Yea, I got errors in simulation.

And I know if I call a memory megafunction from Altera, the module for reading and writing could take more than 1 cyle to do them.

But what if I only need to synthesize a code which can do read in one cycle and do write in one cycle?