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Altera_Forum's avatar
Altera_Forum
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15 years ago

How to write a verilog memory code with a inout data port

Hi all, I was trying to write a verilog code for a memory module which has has a bidirectional inout port for the data. But I also want to output high impedance during write or if MEM_OE(out...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I just renamed MEM_Data to MEM_Data_Bidir.

I did nothing with sources. Only compile it in QuartusII9.1 and simulate.

If you remove data_out register and make output like this:

assign MEM_DATA_bidir = Read ? Memory[address] : 'z ;

then compilator will not optimise regs to memory. But anyway I didn't get one clock read operation.