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Altera_Forum
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15 years ago

How to write a verilog memory code with a inout data port

Hi all, I was trying to write a verilog code for a memory module which has has a bidirectional inout port for the data. But I also want to output high impedance during write or if MEM_OE(out...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

And there was a warning for this code after i did the compilation

Warning: Inferred dual-clock RAM node "Memory~0" from synchronous design logic. The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design.

Will this be where the problem comes from? How could I edit my code to avoid that?