how to Simulate Nios II with custom component?

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im new here and my first post, sorry for not being so professional...

I successfully simlated Nios II on modelsim using QSYS and Eclipse (run as "nios ii Modelsim"), but when I add my custom component to Qsys system it cannot generate testbench or simulation model for it.here is the error:

error: matrixmul_0: matrixmul(my custom hardware design) does not support generation for verilog simulation. generation is available for: quartus synthesis.

I red two tutorial "Altera JTAG-to-Avalon-MM Tutorial" and "how to use Avalon-MM Master BFM" but there was not any sign of Nios processor or custom hardware. Now my question is :

-when we have user defined hardware (in verilog or systemverilog) should we put it inside the qsys system(as a Nios peripheral) or ..!? because last time I put it inside nios and get the result from FPGA DE2 board but not in simulation.

-and how to simulate both hardware and software?

regards.

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a) the error you're getting is because your _hw.tcl doesn't specify what files are included in Verilog simulation. Search for SIM_VERILOG in the Quartus handbook http://www.altera.com/literature/hb/qts/qts_qii5v1.pdf For a simple component, just duplicate your synthesis fileset to populate the SIM_VERILOG fileset.

b) when developing a component, I prefer to place the component in an empty Qsys and export it's interfaces and have Qsys attach BFM's to all the interfaces when it generate the testbench. i.e. without NIOS or any other peripherals if they are not needed. I believe this is the approach the material you have already reviewed also discusses. Here is an Altera example: http://www.altera.com/support/examples/design-flow/exm-avalon-verification-ip.html

c) simulating a NIOS and adding software basically consists of compiling your software and creating a .mif file that ModelSim can load in order to initialize the memory contents that the NIOS will execute from. Here is an older appnote describing the process. http://www.altera.com/literature/an/an351.pdf As a whole, I find that process cumbersome and slow (wall clock time) and prefer BFM's instead of NIOS.

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a) the error you're getting is because your _hw.tcl doesn't specify what files are included in Verilog simulation. Search for SIM_VERILOG in the Quartus handbook http://www.altera.com/literature/hb/qts/qts_qii5v1.pdf For a simple component, just duplicate your synthesis fileset to populate the SIM_VERILOG fileset.

b) when developing a component, I prefer to place the component in an empty Qsys and export it's interfaces and have Qsys attach BFM's to all the interfaces when it generate the testbench. i.e. without NIOS or any other peripherals if they are not needed. I believe this is the approach the material you have already reviewed also discusses. Here is an Altera example: http://www.altera.com/support/examples/design-flow/exm-avalon-verification-ip.html

c) simulating a NIOS and adding software basically consists of compiling your software and creating a .mif file that ModelSim can load in order to initialize the memory contents that the NIOS will execute from. Here is an older appnote describing the process. http://www.altera.com/literature/an/an351.pdf As a whole, I find that process cumbersome and slow (wall clock time) and prefer BFM's instead of NIOS.

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Thanx ted for your nice reply, this problem solved, but i think I have bigger fundamental problem.

my end objective is to simulate a whole SoC system on Modelsim. I mean on one side I should have C code running on NIOS while communicating with other side which is my hardware Component written in Verilog.(that is my own understanding ).

But in those tutorials only we can talk to our component by using OOP programming in SystemVerilog and there is no processor and C code at all!

What am I missing here?

thanks in advance.

Thanks ted for your nice reply, my problem solved. but i think I have fundamental problem.

My end objective is to simulate the whole SoC sistem on Modelsim. It means that C code running on the Nios processor should talk to my custom hardware component. So far I know how to talk to my component (using SystemVerilog OOP programming in the testbench) and in another tutorial I also learned how to simulate the Nios behavior running C code.

But as I mentioned I need to talk to my component through C code running on Nios, Something exactly like this tutorial but in simulation:

https://www.youtube.com/watch?v=ajyyi12yio4

when I simulate this youtube tutorial I get this error:

Loading nios2_inst_altpll_locked_conduit_bfm.altera_conduit_bfm_0002

# Error loading design

I tried to export PLL_conduits but it didnt work.Do I need any other component in my Qsys system?Attached file is my Qsys system.

thanks.https://www.alteraforum.com/forum/attachment.php?attachmentid=9948

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in another tutorial I also learned how to simulate the Nios behavior running C code.

But as I mentioned I need to talk to my component through C code running on Nios

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Take the project that you learned how to simulate NIOS running C code, and just add your component and change your C code. It should be very simple to do.

Regarding your PLL simulation problem, I'm not sure what that is, but for what it's worth: try to avoid adding PLL's in your simulation-only-projects. Just declare new Clock Source's with your defined frequencies and let Qsys take care of it (instead of having Modelsim simulate PLL logic).

Thanks ted. its working now.

But how to keep track of NIOS instruction executions.I want to see what is happening inside and which instruction is going to be executed at each clk cycle? I red somewhere that instruction executed on Nios in simulation is gonna saved in (.tr) file.but i couldnt find this file in my project folder.

can you give me a clue.

thanks again.

To the best of my knowledge, there are not any additional tools to support you. Beyond setting the NIOS running your program, there isn't a lot you can do without additional labor on your part.

You can inspect the nets inside the NIOS instance and observe the program counter, what opcode has been decoded, the instruction/data bus activity, etc.

Determining what file+line of C code is being executed during Modelsim simulation is probably do-able via Modelsim TCL and some offline processing, but will take some work.

If traffic on this forum is an indicator, NIOS simulation is not commonly done beyond the level which you have already achieved (i.e. consider moving to hardware).

Very good ,this step is completed,Thanks ,

Now im tiring to simulate my custom design(without NIOS) using the testbenches lik what it is done in "Altera JTAG-to-Avalon-MM Tutorial".

my custom component is like this (slave):

https://www.alteraforum.com/forum/attachment.php?attachmentid=10031

last time I used this method to talk to my hardware from NIOS:

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# include<stdio.h>

# include<unistd.h>

# include "system.h"

# include "alt_types.h"

# include <io.h>

# ifndef loadstart

# define loadstart 0x0

# endif

# ifndef loadnxt

# define loadnxt 0x1

# endif

# ifndef loadwe

# define loadwe 0x2

# endif

# ifndef loadeaddr

# define loadeaddr 0x3

# endif

# ifndef loadAi0

# define loadAi0 0x4

# endif

# ifndef loadAi1

# define loadAi1 0x5

# endif

# ifndef loadAi2

# define loadAi2 0x6

# endif

# ifndef loadAi3

# define loadAi3 0x7

# endif

# ifndef loadBi0

# define loadBi0 0x8

# endif

# ifndef loadBi1

# define loadBi1 0x9

# endif

# ifndef loadBi2

# define loadBi2 0xA

# endif

# ifndef loadBi3

# define loadBi3 0xB

# endif

# ifndef readsum

# define readsum 0xC

# endif

# ifndef readpdone

# define readpdone 0xD

# endif

# ifndef readdone

# define readdone 0xE

# endif

void matrixmul(int A[16][16],int B[16][16],int C[16][16])

{ int k=0;

IOWR(MATRIXMUL_0_BASE,loadwe,1);

int i,l,m;

for(i=0; i<16; i++)

{

int j=0;

while(j<16)

{

IOWR(MATRIXMUL_0_BASE,loadeaddr,k);

IOWR(MATRIXMUL_0_BASE, loadAi0, A[j]);

iowr(matrixmul_0_base, loadai1, a[j+1]);

IOWR(MATRIXMUL_0_BASE, loadAi2, A[j+2]);

iowr(matrixmul_0_base, loadai3, a[j+3]);;

IOWR(MATRIXMUL_0_BASE, loadBi0, B[j]);

iowr(matrixmul_0_base, loadbi1, b[j+1]);

IOWR(MATRIXMUL_0_BASE, loadBi2, B[j+2]);

iowr(matrixmul_0_base, loadbi3, b[j+3]);

...

...

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But Now I dont know how to communicate with my custom hardware in testbench using "avalon_write" or "avalon_read" since I need to access this signals directly:

input [2:0] address;

input [31:0] writedata;

Now I manipulate avalon_write function and used index of "set_command_data" as below:

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$display("");

test_number = test_number + 1;

$display("-----------------------------------------------");

$display("%1d: Test the GCD.", test_number);

$display("-----------------------------------------------");

// --------------------------------------------------------

//

$display(" * Write 25 to the GCD");

wrdata = 2;

wrindex=1;

avalon_GCD_write('h20, 2,1);

avalon_GCD_write('h20, 25,2);

avalon_GCD_write('h20, 5,3);

avalon_GCD_write('h20, 1,1);

//avalon_GCD_write('h20, wrdata,wrindex);

//avalon_GCD_write('h20, wrdata,wrindex);

for (int i = 0; i < 32; i++)

begin

avalon_read('h20+i, rddata);

$display(" - GCD register value = %.2Xh", rddata);

end

$display("");

---------------------------------------------------------------

task avalon_GCD_write (

// ------------------------------------------------------------

input [`AV_ADDRESS_W-1:0] addr,

input [`AV_DATA_W-1:0] data,

input int index1

);

begin

// Construct the BFM request

`BFM.set_command_request(REQ_WRITE);//fix

`BFM.set_command_idle(0, 0); // idle cycle at the end of each transaction,index?

`BFM.set_command_init_latency(0); //fix Sets the number of cycles to postpone the start of a command.

`BFM.set_command_address(addr); //fix

`BFM.set_command_byte_enable('1,0); // Sets the transaction byte enable,index??

`BFM.set_command_data(data, index1);

// Queue the command

`BFM.push_command();

// Wait until the transaction has completed

while (`BFM.get_response_queue_size() != 1)

@(posedge clk);

// Dequeue the response and discard

`BFM.pop_response();

end

endtask

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but i got this error:2330000: ERROR: qsys_system_bfm_master_tb.dut.bfm_master.__check_transaction_index: Cycle index 1 exceeds MAX_BURST_SIZE-1 0

Totally I dont know what am i doing! but I couldn't find any example in "Introduction to Avalon Verification IP Suite" to how to talk to my custom component. especially I need to access "address" in my own custom component.

can you show me a good tutorial or tell me what to do?

thanks

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Totally I dont know what am i doing!

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At the beginning of your simulation, the Avalon-MM BFM master prints a "Hello!" message. Read it. That should tell you whether you have bursting enabled. Chances are you have not, and you've somehow managed to create an Avalon-MM transaction that is a burst.

Cheers,

Dave

Here is the massage I got:

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run -a

# 0: INFO: qsys_system_bfm_master_tb.dut.bfm_master.__hello: - Hello from altera_avalon_mm_master_bfm

# 0: INFO: qsys_system_bfm_master_tb.dut.bfm_master.__hello: - $Revision:# 1 $

# 0: INFO: qsys_system_bfm_master_tb.dut.bfm_master.__hello: - $Date: 2014/02/16 $

# 0: INFO: qsys_system_bfm_master_tb.dut.bfm_master.__hello: - AV_ADDRESS_W = 32

# 0: INFO: qsys_system_bfm_master_tb.dut.bfm_master.__hello: - AV_SYMBOL_W = 8

# 0: INFO: qsys_system_bfm_master_tb.dut.bfm_master.__hello: - AV_NUMSYMBOLS = 4

# 0: INFO: qsys_system_bfm_master_tb.dut.bfm_master.__hello: - AV_BURSTCOUNT_W = 3

# 0: INFO: qsys_system_bfm_master_tb.dut.bfm_master.__hello: - REGISTER_WAITREQUEST = 0

# 0: INFO: qsys_system_bfm_master_tb.dut.bfm_master.__hello: - AV_FIX_READ_LATENCY = 1

# 0: INFO: qsys_system_bfm_master_tb.dut.bfm_master.__hello: - AV_MAX_PENDING_READS = 0

# 0: INFO: qsys_system_bfm_master_tb.dut.bfm_master.__hello: - AV_MAX_PENDING_WRITES = 0

# 0: INFO: qsys_system_bfm_master_tb.dut.bfm_master.__hello: - USE_READ = 1

# 0: INFO: qsys_system_bfm_master_tb.dut.bfm_master.__hello: - USE_WRITE = 1

# 0: INFO: qsys_system_bfm_master_tb.dut.bfm_master.__hello: - USE_ADDRESS = 1

# 0: INFO: qsys_system_bfm_master_tb.dut.bfm_master.__hello: - USE_BYTE_ENABLE = 1

# 0: INFO: qsys_system_bfm_master_tb.dut.bfm_master.__hello: - USE_BURSTCOUNT = 0

# 0: INFO: qsys_system_bfm_master_tb.dut.bfm_master.__hello: - USE_READ_DATA = 1

# 0: INFO: qsys_system_bfm_master_tb.dut.bfm_master.__hello: - USE_READ_DATA_VALID = 1

# 0: INFO: qsys_system_bfm_master_tb.dut.bfm_master.__hello: - USE_WRITE_DATA = 1

# 0: INFO: qsys_system_bfm_master_tb.dut.bfm_master.__hello: - USE_BEGIN_TRANSFER = 0

# 0: INFO: qsys_system_bfm_master_tb.dut.bfm_master.__hello: - USE_BEGIN_BURST_TRANSFER = 0

# 0: INFO: qsys_system_bfm_master_tb.dut.bfm_master.__hello: - USE_WAIT_REQUEST = 1

# 0: INFO: qsys_system_bfm_master_tb.dut.bfm_master.__hello: - USE_LOCK = 0

# 0: INFO: qsys_system_bfm_master_tb.dut.bfm_master.__hello: - USE_DEBUGACCESS = 0

# 0: INFO: qsys_system_bfm_master_tb.dut.bfm_master.__hello: - USE_TRANSACTIONID = 0

# 0: INFO: qsys_system_bfm_master_tb.dut.bfm_master.__hello: - USE_WRITERESPONSE = 0

# 0: INFO: qsys_system_bfm_master_tb.dut.bfm_master.__hello: - USE_READRESPONSE = 0

# 0: INFO: qsys_system_bfm_master_tb.dut.bfm_master.__hello: - USE_CLKEN = 0

# 0: INFO: ------------------------------------------------------------

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and then the simulation results:

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===============================================================

# JTAG-to-Avalon-MM SOPC System Testbench (using the BFM master)

# ===============================================================

#

# 0: verbosity_pkg.set_verbosity: Setting Verbosity level=4 (VERBOSITY_INFO)

# * Deassert reset

#

# -----------------------------------------------

# 1: Test the LEDs.

# -----------------------------------------------

# * Write 0xAA to the LEDs

# - LED register value = aah

# - LED port value = aah

# * Walking 1's test

# - LED port value = 01h

# - LED port value = 02h

# - LED port value = 04h

# - LED port value = 08h

# - LED port value = 10h

# - LED port value = 20h

# - LED port value = 40h

# - LED port value = 80h

#

# -----------------------------------------------

# 2: Test the push buttons.

# -----------------------------------------------

# * Push button value = 55h

# * Walking 1's test

# - Push button value = 01h

# - Push button value = 02h

# - Push button value = 04h

# - Push button value = 08h

# - Push button value = 10h

# - Push button value = 20h

# - Push button value = 40h

# - Push button value = 80h

#

# -----------------------------------------------

# 3: Test the GCD.

# -----------------------------------------------

# * Write 25 to the GCD

# 2330000: ERROR: qsys_system_bfm_master_tb.dut.bfm_master.__check_transaction_index: Cycle index 1 exceeds MAX_BURST_SIZE-1 0

# 2330000: FAILURE: verbosity_pkg.abort_simulation: Abort the simulation due to fatal error incident.

# ** Note: $finish : ./..//submodules/verbosity_pkg.sv(185)

# Time: 2330 ns Iteration: 1 Instance: /qsys_system_bfm_master_tb/dut/bfm_master

# 1

# Break in Function abort_simulation at ./..//submodules/verbosity_pkg.sv line 185

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The fact that USE_BURSTCOUNT = 0 indicates that you have not enabled bursting.

Its a little difficult to help you without you posting the code.

Please do not post it inline though, just attach the testcase code as a file and I'll take a look.

Cheers,

Dave