how to Simulate Nios II with custom component?

--- Quote Start ---

im new here and my first post, sorry for not being so professional...

I successfully simlated Nios II on modelsim using QSYS and Eclipse (run as "nios ii Modelsim"), but when I add my custom component to Qsys system it cannot generate testbench or simulation model for it.here is the error:

error: matrixmul_0: matrixmul(my custom hardware design) does not support generation for verilog simulation. generation is available for: quartus synthesis.

I red two tutorial "Altera JTAG-to-Avalon-MM Tutorial" and "how to use Avalon-MM Master BFM" but there was not any sign of Nios processor or custom hardware. Now my question is :

-when we have user defined hardware (in verilog or systemverilog) should we put it inside the qsys system(as a Nios peripheral) or ..!? because last time I put it inside nios and get the result from FPGA DE2 board but not in simulation.

-and how to simulate both hardware and software?

regards.

--- Quote End ---

a) the error you're getting is because your _hw.tcl doesn't specify what files are included in Verilog simulation. Search for SIM_VERILOG in the Quartus handbook http://www.altera.com/literature/hb/qts/qts_qii5v1.pdf For a simple component, just duplicate your synthesis fileset to populate the SIM_VERILOG fileset.

b) when developing a component, I prefer to place the component in an empty Qsys and export it's interfaces and have Qsys attach BFM's to all the interfaces when it generate the testbench. i.e. without NIOS or any other peripherals if they are not needed. I believe this is the approach the material you have already reviewed also discusses. Here is an Altera example: http://www.altera.com/support/examples/design-flow/exm-avalon-verification-ip.html

c) simulating a NIOS and adding software basically consists of compiling your software and creating a .mif file that ModelSim can load in order to initialize the memory contents that the NIOS will execute from. Here is an older appnote describing the process. http://www.altera.com/literature/an/an351.pdf As a whole, I find that process cumbersome and slow (wall clock time) and prefer BFM's instead of NIOS.