im new here and my first post, sorry for not being so professional... I successfully simlated Nios II on modelsim using QSYS and Eclipse (run as "nios ii Modelsim"), but when I add my custom component to Qsys system it cannot generate testbench or simulation model for it.here is the error: error: matrixmul_0: matrixmul(my custom hardware design) does not support generation for verilog simulation. generation is available for: quartus synthesis.&#65279; I red two tutorial "Altera JTAG-to-Avalon-MM Tutorial" and "how to use Avalon-MM Master BFM" but there was not any sign of Nios processor or custom hardware. Now my question is : -when we have user defined hardware (in verilog or systemverilog) should we put it inside the qsys system(as a Nios peripheral) or ..!? because last time I put it inside nios and get the result from FPGA DE2 board but not in simulation. -and how to simulate both hardware and software? regards.

--- Quote Start --- im new here and my first post, sorry for not being so professional... I successfully simlated Nios II on modelsim using QSYS and Eclipse (run as "nios ii Modelsim"), but when I add my custom component to Qsys system it cannot generate testbench or simulation model for it.here is the error: error: matrixmul_0: matrixmul(my custom hardware design) does not support generation for verilog simulation. generation is available for: quartus synthesis.&#65279; I red two tutorial "Altera JTAG-to-Avalon-MM Tutorial" and "how to use Avalon-MM Master BFM" but there was not any sign of Nios processor or custom hardware. Now my question is : -when we have user defined hardware (in verilog or systemverilog) should we put it inside the qsys system(as a Nios peripheral) or ..!? because last time I put it inside nios and get the result from FPGA DE2 board but not in simulation. -and how to simulate both hardware and software? regards. --- Quote End --- a) the error you're getting is because your _hw.tcl doesn't specify what files are included in Verilog simulation. Search for SIM_VERILOG in the Quartus handbook http://www.altera.com/literature/hb/qts/qts_qii5v1.pdf For a simple component, just duplicate your synthesis fileset to populate the SIM_VERILOG fileset. b) when developing a component, I prefer to place the component in an empty Qsys and export it's interfaces and have Qsys attach BFM's to all the interfaces when it generate the testbench. i.e. without NIOS or any other peripherals if they are not needed. I believe this is the approach the material you have already reviewed also discusses. Here is an Altera example: http://www.altera.com/support/examples/design-flow/exm-avalon-verification-ip.html c) simulating a NIOS and adding software basically consists of compiling your software and creating a .mif file that ModelSim can load in order to initialize the memory contents that the NIOS will execute from. Here is an older appnote describing the process. http://www.altera.com/literature/an/an351.pdf As a whole, I find that process cumbersome and slow (wall clock time) and prefer BFM's instead of NIOS.

--- Quote Start --- a) the error you're getting is because your _hw.tcl doesn't specify what files are included in Verilog simulation. Search for SIM_VERILOG in the Quartus handbook http://www.altera.com/literature/hb/qts/qts_qii5v1.pdf For a simple component, just duplicate your synthesis fileset to populate the SIM_VERILOG fileset. b) when developing a component, I prefer to place the component in an empty Qsys and export it's interfaces and have Qsys attach BFM's to all the interfaces when it generate the testbench. i.e. without NIOS or any other peripherals if they are not needed. I believe this is the approach the material you have already reviewed also discusses. Here is an Altera example: http://www.altera.com/support/examples/design-flow/exm-avalon-verification-ip.html c) simulating a NIOS and adding software basically consists of compiling your software and creating a .mif file that ModelSim can load in order to initialize the memory contents that the NIOS will execute from. Here is an older appnote describing the process. http://www.altera.com/literature/an/an351.pdf As a whole, I find that process cumbersome and slow (wall clock time) and prefer BFM's instead of NIOS. --- Quote End --- Thanx ted for your nice reply, this problem solved, but i think I have bigger fundamental problem. my end objective is to simulate a whole SoC system on Modelsim. I mean on one side I should have C code running on NIOS while communicating with other side which is my hardware Component written in Verilog.(that is my own understanding ). But in those tutorials only we can talk to our component by using OOP programming in SystemVerilog and there is no processor and C code at all! What am I missing here? thanks in advance.

Thanks ted for your nice reply, my problem solved. but i think I have fundamental problem. My end objective is to simulate the whole SoC sistem on Modelsim. It means that C code running on the Nios processor should talk to my custom hardware component. So far I know how to talk to my component (using SystemVerilog OOP programming in the testbench) and in another tutorial I also learned how to simulate the Nios behavior running C code. But as I mentioned I need to talk to my component through C code running on Nios, Something exactly like this tutorial but in simulation: https://www.youtube.com/watch?v=ajyyi12yio4 when I simulate this youtube tutorial I get this error: Loading nios2_inst_altpll_locked_conduit_bfm.altera_conduit_bfm_0002 # Error loading design I tried to export PLL_conduits but it didnt work.Do I need any other component in my Qsys system?Attached file is my Qsys system. thanks.https://www.alteraforum.com/forum/attachment.php?attachmentid=9948

--- Quote Start --- in another tutorial I also learned how to simulate the Nios behavior running C code. But as I mentioned I need to talk to my component through C code running on Nios --- Quote End --- Take the project that you learned how to simulate NIOS running C code, and just add your component and change your C code. It should be very simple to do. Regarding your PLL simulation problem, I'm not sure what that is, but for what it's worth: try to avoid adding PLL's in your simulation-only-projects. Just declare new Clock Source's with your defined frequencies and let Qsys take care of it (instead of having Modelsim simulate PLL logic).

Thanks ted. its working now. But how to keep track of NIOS instruction executions.I want to see what is happening inside and which instruction is going to be executed at each clk cycle? I red somewhere that instruction executed on Nios in simulation is gonna saved in (.tr) file.but i couldnt find this file in my project folder. can you give me a clue. thanks again.

how to Simulate Nios II with custom component?

19 Replies

Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---
The fact that USE_BURSTCOUNT = 0 indicates that you have not enabled bursting.

Its a little difficult to help you without you posting the code.

Please do not post it inline though, just attach the testcase code as a file and I'll take a look.

Cheers,
Dave
--- Quote End ---

I got My code from tutorial "Altera JTAG-to-Avalon-MM Tutorial", and couldnt use "ug_avalon_verification_ip" document properly.
attached file is testcase code:

Tanks.
qsys_system_bfm_master_tb_sv.txt10 KB
Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---
I got My code from tutorial "Altera JTAG-to-Avalon-MM Tutorial"

--- Quote End ---

Yeah, I know, I recognize the code (I wrote it). What I don't understand is why you decided you had to create the task avalon_GCD_write and change the data line `BFM.set_command_data(data, index1);

What are you trying to do with index1 - that is the source of your error. You are indicating to the BFM that the data is a burst, and at index1 here is the data. If index1 is 0, then its fine, but any other value is wrong, since your BFM is not configured for bursts.

For example, what are you trying to do here?
avalon_GCD_write('h20, 2,1); avalon_GCD_write('h20, 25,2); avalon_GCD_write('h20, 5,3); avalon_GCD_write('h20, 1,1);

If you are trying to address different registers, relative to the base address of 'h20, then simply change the address by the number of bytes the addresses are spaced, eg. assuming 32-bit registers for each location you would write

avalon_write('h24, 2); avalon_write('h28, 25); avalon_write('h2C, 5); avalon_write('h24, 1);

or if you prefer
int gcd_base = 'h20; avalon_write(gcd_base + 'h04, 2); avalon_write(gcd_base + 'h08, 25); avalon_write(gcd_base + 'h0C, 5); avalon_write(gcd_base + 'h04, 1);

Hopefully that makes a little more sense now.

Cheers,
Dave
Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---
To the best of my knowledge, there are not any additional tools to support you. Beyond setting the NIOS running your program, there isn't a lot you can do without additional labor on your part.

You can inspect the nets inside the NIOS instance and observe the program counter, what opcode has been decoded, the instruction/data bus activity, etc.

Determining what file+line of C code is being executed during Modelsim simulation is probably do-able via Modelsim TCL and some offline processing, but will take some work.

If traffic on this forum is an indicator, NIOS simulation is not commonly done beyond the level which you have already achieved (i.e. consider moving to hardware).
--- Quote End ---

Do you know why im getting this error in Modelsim_Nios Simulation:

--- Quote Start ---
# Warning: read_during_write_mode_mixed_ports is assumed as OLD_DATA# Time: 0 Instance: nios2_tb.nios2_inst.nios2.niil1ii.genblk1.altsyncram_inst# 0: INFO: nios2_tb.nios2_inst_clk_bfm.__hello: - Hello from altera_clock_source.# 0: INFO: nios2_tb.nios2_inst_clk_bfm.__hello: - $Revision:# 1 $# 0: INFO: nios2_tb.nios2_inst_clk_bfm.__hello: - $Date: 2014/02/16 $# 0: INFO: nios2_tb.nios2_inst_clk_bfm.__hello: - CLOCK_RATE = 50000000 Hz# 0: INFO: ------------------------------------------------------------# # ===============================================================# Testing the Software implementation of GCD# ===============================================================# # - GCD (Warning : Address pointed at port A is out of bound!# Time: 1105670000 Instance: nios2_tb.nios2_inst.onchip_memory.the_altsyncram.genblk1.altsyncram_inst# warning : address pointed at port a is out of bound!# Time: 1105670000 Instance: nios2_tb.nios2_inst.onchip_memory.the_altsyncram.genblk1.altsyncram_inst# 20 ,Warning : Address pointed at port A is out of bound!# Time: 1161730000 Instance: nios2_tb.nios2_inst.onchip_memory.the_altsyncram.genblk1.altsyncram_inst# Warning : Address pointed at port A is out of bound!# Time: 1161730000 Instance: nios2_tb.nios2_inst.onchip_memory.the_altsyncram.genblk1.altsyncram_inst# 10) =Warning : Address pointed at port A is out of bound!# Time: 1217650000 Instance: nios2_tb.nios2_inst.onchip_memory.the_altsyncram.genblk1.altsyncram_inst# Warning : Address pointed at port A is out of bound!# Time: 1217650000 Instance: nios2_tb.nios2_inst.onchip_memory.the_altsyncram.genblk1.altsyncram_inst
10

--- Quote End ---

I have no idea what is port A!, but i try to printf different type of variables (int (%d), short int ...) but still i got the same error.
I tried to stop that using Modelsim commands:"set StdArithNoWarnings 1 ,set NumericStdNoWarnings 1" but it didnt work.
thanks
Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---

I have no idea what is port A

--- Quote End ---

Its your design, learn to read code :)

Its likely that the component nios2_tb.nios2_inst.onchip_memory.the_altsyncram is dual-ported RAM, and you are generating addresses that are "out of bound!". Search the source code using a "find in files" tool (Textpad has one), and chances are you'll find it in the altsyncram component. Either way, you can probably probe the port A address of the altsyncram and see what addresses are being generated to cause the warning.

Cheers,
Dave
Altera_Forum
Honored Contributor
11 years ago
Ya, it was on chip memory, I increase the size to 512k and it is working properly,
thanks.:cool:
Altera_Forum
Honored Contributor
11 years ago
Now I changed my custom hardware to convolution filter that needs stream data from NIOS. But i don't know which Buffer to chose in QSYS system. I think Avalon_ST Dual Clock FIFO should work since my custom disign is much faster than the NIOS frequency.
My problem is that i couldn't find any simple code example out there that shows how to save data to fifo and how to read from.
I would appreciate if anyone give me some simple read-write-fifo code.
thanks
Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---

... needs stream data from NIOS

--- Quote End ---

Look at the SGDMA controller. I believe you can configure it to DMA from an Avalon-MM source (memory) to an Avalon-ST stream, and from an Avalon-ST stream to Avalon-MM memory. You would use the DMA controller as your Avalon-ST source and Avalon-ST sink, and connect your convolution filter to those ports.

If you have questions about the SGDMA controller, post a new thread, I haven't used it, so cannot help with it.

Cheers,
Dave
Altera_Forum
Honored Contributor
11 years ago
Sorry can you please specifically show me the link for the example you mentioned ,
thanks.
Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---
Sorry can you please specifically show me the link for the example you mentioned
--- Quote End ---

This is the component I am referring to;

http://www.alterawiki.com/wiki/modular_sgdma

As the wiki states, its now a standard Qsys component, so you should be able to find it in Qsys. For example, I just started Quartus 14.0, then selected Tools->Qsys, and then typed "dma" into the IP Catalog search bar, and a component with this name shows up. Read the wiki documentation to get an idea of how to use it.

Post a new thread if you need help with it. I think one of the forum members wrote it, so if they see a thread with SGDMA in the title, they'll likely help.

Cheers,
Dave

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how to Simulate Nios II with custom component?

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