--- Quote Start ---
a) the error you're getting is because your _hw.tcl doesn't specify what files are included in Verilog simulation. Search for SIM_VERILOG in the Quartus handbook
http://www.altera.com/literature/hb/qts/qts_qii5v1.pdf For a simple component, just duplicate your synthesis fileset to populate the SIM_VERILOG fileset.
b) when developing a component, I prefer to place the component in an empty Qsys and export it's interfaces and have Qsys attach BFM's to all the interfaces when it generate the testbench. i.e. without NIOS or any other peripherals if they are not needed. I believe this is the approach the material you have already reviewed also discusses. Here is an Altera example:
http://www.altera.com/support/examples/design-flow/exm-avalon-verification-ip.html c) simulating a NIOS and adding software basically consists of compiling your software and creating a .mif file that ModelSim can load in order to initialize the memory contents that the NIOS will execute from. Here is an older appnote describing the process.
http://www.altera.com/literature/an/an351.pdf As a whole, I find that process cumbersome and slow (wall clock time) and prefer BFM's instead of NIOS.
--- Quote End ---
Thanx ted for your nice reply, this problem solved, but i think I have bigger fundamental problem.
my end objective is to simulate a whole SoC system on Modelsim. I mean on one side I should have C code running on NIOS while communicating with other side which is my hardware Component written in Verilog.(that is my own understanding ).
But in those tutorials only we can talk to our component by using OOP programming in SystemVerilog and there is no processor and C code at all!
What am I missing here?
thanks in advance.
Honored Contributor
