Forum Discussion
Altera_Forum
Honored Contributor
11 years agoThanks ted for your nice reply, my problem solved. but i think I have fundamental problem.
My end objective is to simulate the whole SoC sistem on Modelsim. It means that C code running on the Nios processor should talk to my custom hardware component. So far I know how to talk to my component (using SystemVerilog OOP programming in the testbench) and in another tutorial I also learned how to simulate the Nios behavior running C code. But as I mentioned I need to talk to my component through C code running on Nios, Something exactly like this tutorial but in simulation: https://www.youtube.com/watch?v=ajyyi12yio4 when I simulate this youtube tutorial I get this error: Loading nios2_inst_altpll_locked_conduit_bfm.altera_conduit_bfm_0002 # Error loading design I tried to export PLL_conduits but it didnt work.Do I need any other component in my Qsys system?Attached file is my Qsys system. thanks.https://www.alteraforum.com/forum/attachment.php?attachmentid=9948