Altera_Forum
Honored Contributor
9 years agoHow to know or test the delay time of each logic unit
I am making delay line to implement the TDC. I tried to use buffers to make the delay line and want to know the delay time of each buffer element. But when I use the TimeQuest to report the path delay, it seems that no matter how many buffers I add, the delay times are the same. For example, I use 8 buffers and 4 buffers separately, the pictures and report are showed below.
http://www.alteraforum.com/forum/attachment.php?attachmentid=13069&stc=1 http://www.alteraforum.com/forum/attachment.php?attachmentid=13070&stc=1 http://www.alteraforum.com/forum/attachment.php?attachmentid=13071&stc=1 I guess because the IO buffers consume two much time compared to the buffers B-I (B-E), so the delay time of the buffers are ignored. So, my question is how to know the delay time of each logic unit in a specific FPGA family? For example, if I use buffers, then the delay time of each buffer must be known, and if I use the carry line to make the delay line, I must know the delay time of each adder. Thanks for any help.