How to know or test the delay time of each logic unit

Have you checked that quartus hasnt reduced your logic into a single wire? unless you explicitly ask it not to, it will reduce all buffers like this. You can do this via the keep attribute in your HDL.

The next problem is that while timequest can give you the worst case delay, the timing delay through all logic elements in modern FPGAs is very small to start with, and then they vary with PVT - process, voltage and temperature, so it is very difficult or impossible to get a known time delay through logic. FPGAs are designed around a synchronous archutecture.