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Altera_Forum
Honored Contributor
9 years agoHow to know or test the delay time of each logic unit
I am making delay line to implement the TDC. I tried to use buffers to make the delay line and want to know the delay time of each buffer element. But when I use the TimeQuest to report the path dela...
Altera_Forum
Honored Contributor
9 years agoWhat order of length for signals are you expecting? can you not just run a fast clock and measure the length of a signal using a counter?