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Altera_Forum's avatar
Altera_Forum
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10 years ago

How to implement testbench for VHDL Output File (.vho)

I am verifying a design where i dont have source code but VHDL Output File .vho and few snapshots of block diagram. I have located .vho file in my project folder and simply run via double clicking. There i have command line interface of ModelSim where i run .do file (TCL commands writen in that file). And input/output signals can be observed over WAVE window. But i need to write testbench for the same but i dont know method for instantiating the top level in my testbench and then compile and run the same. It can be easily done when i have source code but i don't know how to include my top_level_design which is already been compiled separately and i am left with VHDL Output File (.vho)

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Is the design done in block diagram files? if you have no source, then simulating it wouldnt be much use anyway, as you wouldnt be able to compile the design in quartus. If it's all in block diagram files, then you can convert each file to VHDL by going to file -> convert -> vhdl.

    This way you then have the source.

    What is it that stimulates the design in the .vho file?
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Thanks tricky.

    Yes the design was partially done in block diagram. So should i convert each and every dbf and bsf into .vhd then create a new project in modelsim, add every .vhd file in project then compile it?? then i have my source code that can be simulate via testbench ??

    I am using .vho file to perform Functional Verification via TCL scripting because i dont know any other way.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    you only need to convert the bdf files - bsf are just symbol files used in the bdf files. When you have vhd for everything, then yes, you can use a testbench like normal.

    This is one reason it's recommended to only use HDL for design.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Well said tricky. I did as you suggested converted all the bdf to vhd and then compile them all. Only the top level giving me 200+ errors rest of modules got compiled successfully in a blink.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Thanks tricky for your advise. I have removed all errors and now i have full compilation of my code. Although i have many warnings left to remove. The problem was with the quartus converter that converted bdf to vhdl code. Many vector signals were split into single bit and they all drive the same wire at the same time. It took all the careful manual observation to find them and clear them.