How to implement testbench for VHDL Output File (.vho)

Thanks tricky for your advise. I have removed all errors and now i have full compilation of my code. Although i have many warnings left to remove. The problem was with the quartus converter that converted bdf to vhdl code. Many vector signals were split into single bit and they all drive the same wire at the same time. It took all the careful manual observation to find them and clear them.