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Honored Contributor
Honored ContributorHow to implement testbench for VHDL Output File (.vho)
I am verifying a design where i dont have source code but VHDL Output File .vho and few snapshots of block diagram. I have located .vho file in my project folder and simply run via double clicking. ...
Altera_ForumHonored Contributor
Honored Contributoryou only need to convert the bdf files - bsf are just symbol files used in the bdf files. When you have vhd for everything, then yes, you can use a testbench like normal.
This is one reason it's recommended to only use HDL for design.
