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Altera_Forum
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10 years ago

How to implement testbench for VHDL Output File (.vho)

I am verifying a design where i dont have source code but VHDL Output File .vho and few snapshots of block diagram. I have located .vho file in my project folder and simply run via double clicking. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Well said tricky. I did as you suggested converted all the bdf to vhd and then compile them all. Only the top level giving me 200+ errors rest of modules got compiled successfully in a blink.