How to implement testbench for VHDL Output File (.vho)

Thanks tricky.

Yes the design was partially done in block diagram. So should i convert each and every dbf and bsf into .vhd then create a new project in modelsim, add every .vhd file in project then compile it?? then i have my source code that can be simulate via testbench ??

I am using .vho file to perform Functional Verification via TCL scripting because i dont know any other way.