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Honored Contributor
Honored ContributorHow to implement testbench for VHDL Output File (.vho)
I am verifying a design where i dont have source code but VHDL Output File .vho and few snapshots of block diagram. I have located .vho file in my project folder and simply run via double clicking. ...
Altera_ForumHonored Contributor
Honored ContributorIs the design done in block diagram files? if you have no source, then simulating it wouldnt be much use anyway, as you wouldnt be able to compile the design in quartus. If it's all in block diagram files, then you can convert each file to VHDL by going to file -> convert -> vhdl.
This way you then have the source. What is it that stimulates the design in the .vho file?
