I only know how to do RTL functional simulation (only need HDL files) and GTL timing simulation (need .vo or .vho and .sdo files)in ModelSim. However, how can I do post-synthesis simulation in ModelSim? What type files do I need ? Thanks.

You need to change a setting: http://quartushelp.altera.com/10.1/mergedprojects/eda/quartus2/eda_sim_gen_netlist.htm If you follow this procedure, Quartus will produce a .vo/.vho with the post-synthesis netlist; no .sdo is used here.

Thanks very much, rbugalho. And could you explain to me what is difference between RTL functional simulation and post-synthesis simulation? I searched online but did not get very clear explaination. Thanks.

--- Quote Start --- could you explain to me what is difference between RTL functional simulation and post-synthesis simulation? --- Quote End --- In an RTL simulation, the simulator compiles the VHDL in your components and any simulation models, instantiates that in your testbench and runs. In a post-synthesis simulation, the simulator compiles the netlist generated by the synthesis tool (the Quartus .vho or .vo output file). If you look at that netlist, you'll see its been 'flattened' so its just one huge file. Some of the 'secret sauce' of the FPGA will still be hidden from you using basic components, that Altera calls atoms (that's why you need a different set of libraries for netlist simulation in Modelsim-SE, Modelsim-ASE has them precompiled). The post-synthesis simulation can be run without timing delays. You can use that to check that the top-level waveforms look identical. The simulation can also be run in conjunction with a timing netlist or .SDF file (output as a .sdo file by Quartus). In Modelsim, you use the -sdfxxx command to tell it what kind of timing simulation you want. Generally if your RTL simulation passes when run in a testbench that has good coverage, i.e., the test sequences test each operating mode of the device, and the TimeQuest indicates the design meets timing, then you can just test the design in hardware. If the design does not work, then you can use SignalTap II to see what is going wrong. You can add the SignalTap II sequence to your RTL simulation test case, and see if this is a testcase you missed, or is something specific to the hardware. If it appears to be specific to the hardware, then you can run a post-synthesis simulation, followed by a post-synthesis timing simulation to hopefully reproduce, and then resolve, the issue. I have had to do this type of debugging in the past, but it was a long time ago (Mentor LeonardoSpectrum EDIF placed-and-routed using MAX+Plus II). I have not had to do this type of debugging with Quartus netlists. What type of error does this catch? One example I recall is that the LPM_COUNTER component should have a default value of '1' on its carry-in port, so that it will count up. If you do not use the cin port, then the synthesis tool uses the default port value from the component definition. I forget the exact details, but the synthesis tool either did not use the default, or it did not pass it via the EDIF netlist, and so the counter would not count up in the hardware. This was before SignalTap II existed, but the post-synthesis netlist simulation showed the counter was not working, so pointed me in the direction I needed to look. This gives you an overview as to why there are different netlists. Cheers, Dave

Thanks very much, Dave. In your reply, you mentioned "a post-synthesis timing simulation", do you mean GTL timing simulation? Thanks again.

How to do post-synthesis simulation in ModelSim?

15 Replies

Altera_Forum
Honored Contributor
13 years ago
Hello Dave, I wonder whether you have relevant experience using counter to create clock signals, if you do, could you help me about the following question:

Now I am working on a design which needs different rate clock signals. However, some clock signals can not be achieved directly through PLL in the chip. So I plan to use counter and PLL to achieve the demanded clock signals.

As I know, if I use counter to create a clock signals, there may be some problems. Because the counter output can not guarantee that the counter output signals arrive at different components clock pins at exactly same time, these little time differences in signals arrive may cause serious problem that make the system does not work as expect. I just heard there is a IP core that like global clock, the input is the clock signals like the counter output, the outputs are still clock signals, however the output signals from the global clock can guarantee arriving different components at the exact time to avoid mismatch.

I try to find this IP core in QuartusII but I can't got it. I just wonder who have heard this type IP or used this before? if there is no IP core like I described, how can I handle the issue I describe above about using counter to generate the clock signals?

Thanks very much!
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---

Now I am working on a design which needs different rate clock signals. However, some clock signals can not be achieved directly through PLL in the chip. So I plan to use counter and PLL to achieve the demanded clock signals.

--- Quote End ---
There's two ways to achieve what you want:

1) Use a higher clock rate and an enable signal.

If I have a component that needs to operate at 5MHz, then rather than creating a 5MHz clock, I create a 5MHz enable pulse, and clock at whatever the rest of my design operates at.

Why do it this way? Well, older generations of FPGAs had very limited clock routing, so this was your only option.

2) Use a counter to generate a clock.

This can work, up until the point that you use all the clock routing resources on your FPGA (if you create too many generated clocks).

You use TimeQuest to constrain this type of clock using the create_generated_clock .SDC command.

http://www.altera.com/support/software/timequest/clock/tq-generate-clock.html

Since your generated clock will have a delay relative to the original, you should use clock domain crossing logic between your fast and slow clock domains.

My recommendation would be to use (2) wisely, in that you should try to group all 'slow' devices into one clock domain, and generate a single slow clock, rather than lots. If you were creating a Qsys system, then you would put all of these devices on the other side of a clock-crossing bridge.

Cheers,
Dave
Altera_Forum
Honored Contributor
13 years ago
Thanks very much, Dave. But how can I check how much clock routing resources I have used for the design in my FPGA chip?
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
But how can I check how much clock routing resources I have used for the design in my FPGA chip?
--- Quote End ---

You don't. Quartus will tell you if it runs out. I'm sure there is a report file somewhere that you can look in, but in reality, you do not care. If your design synthesizes and passes timing, then you can test it.

Cheers,
Dave
Altera_Forum
Honored Contributor
13 years ago
Thanks very much, Dave. You are always helpful!

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How to do post-synthesis simulation in ModelSim?

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